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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. o 07/02/2010 copyright ? 2010 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services descri bed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fail ure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. prod ucts are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is63lv1024 is63lv1024l 128k x 8 high-speed cmos static ram 3.3v revolutionary pinout features ? high-speed access times: 8, 10, 12 ns ? high-performance, low-power cmos process ? multiple center power and ground pins for greater noise immunity ? easy memory expansion with ce and oe options ? ce power-down ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single 3.3v power supply ? packages available: ? 32-pin 300-mil soj ? 32-pin 400-mil soj ? 32-pin tsop (type ii) ? 32-pin stsop (type i) ? 36-pin bga (8mmx10mm) ? lead-free available description the issi is63lv1024/is63lv1024l is a very high-speed, low power, 131,072-word by 8-bit cmos static ram in revolutionary pinout. the is63lv1024/is63lv1024l is fab- ricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 w (typical) with cmos input levels. the is63lv1024/is63lv1024l operates from a single 3.3v power supply and all inputs are ttl-compatible. functional block diagram a0-a16 ce oe we 128k x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 july 2010
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. o 07/02/2010 is63lv1024 is63lv1024l pin configuration 32-pin soj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 ce i/o0 i/o1 vdd gnd i/o2 i/o3 we a4 a5 a6 a7 a16 a15 a14 a13 oe i/o7 i/o6 gnd vdd i/o5 i/o4 a12 a11 a10 a9 a8 pin descriptions a0-a16 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 data inputs/outputs v dd power gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 ce i/o0 i/o1 vdd gnd i/o2 i/o3 we a4 a5 a6 a7 a16 a15 a14 a13 oe i/o7 i/o6 gnd vdd i/o5 i/o4 a12 a11 a10 a9 a8 pin configuration 32-pin tsop (type ii) (t) 32-pin stsop (type i) (h) pin configuration 36-mini bga (b) (8 mm x 10 mm) 1 2 3 4 5 6 a b c d e f g h a0 a1 nc a3 a6 a8 i/o4 a2 we a4 a7 i/o 0 i/o5 nc a5 i/o 1 gnd vdd vdd gnd i/o6 nc nc i/o 2 i/o7 oe ce a16 a15 i/o 3 a9 a10 a11 a12 a13 a14
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. o 07/02/2010 is63lv1024 is63lv1024l absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to v dd + 0.5 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table mode we we we we we ce ce ce ce ce oe oe oe oe oe i/o operation v dd current not selected x h x high-z i sb 1 , i sb 2 (power-down) output disabled h l h high-z i cc 1 , i cc 2 read h l l d out i cc 1 , i cc 2 write l l x d in i cc 1 , i cc 2 dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd com. ?1 1 a ind. ?5 5 i lo output leakage gnd v out v dd , outputs disabled com. ?1 1 a ind. ?5 5 note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width under vss < 5ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width over v dd < 5ns). not 100% tested. operating range range ambient temperature v dd commercial 0c to +70c 3.3v 0.3v industrial ?40c to +85c 3.3v 0.15v
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. o 07/02/2010 is63lv1024 is63lv1024l capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. is63lv1024l power supply characteristics (1) (over operating range) -8 ns -10 ns -12 ns symbol parameter test conditions min. max. min. max. min. max. unit i cc 1 v dd operating v dd = max., ce = v il com. ? 100 ? 95 ? 90 ma supply current i out = 0 ma, f = max. ind. ? 110 ? 105 ? 100 typ. (2) ?75 ?70 ?65 i sb ttl standby v dd = max., com. ? 35 ? 30 ? 25 ma current v in = v ih or v il ind. ? 40 ? 35 ? 30 (ttl inputs) ce v ih , f = max i sb 1 ttl standby v dd = max., com. ? 15 ? 15 ? 15 ma current v in = v ih or v il ind. ? 20 ? 20 ? 20 (ttl inputs) ce v ih , f = 0 i sb 2 cmos standby v dd = max., com. ? 1 ? 1 ? 1 ma current ce v dd ? 0.2v, ind. ? 1.5 ? 1.5 ? 1.5 typ. (2) ? 0.05 ? 0.05 ? 0.05 (cmos inputs) v in v dd ? 0.2v, or v in 0.2v, f = 0 notes: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.3v, t a = 25 o c. not 100% tested. is63lv1024 power supply characteristics (1) (over operating range) -8 ns -10 ns -12 ns symbol parameter test conditions min. max. min. max. min. max. unit i cc 1 v dd operating v dd = max., ce = v il com. ? 160 ? 150 ? 130 ma supply current i out = 0 ma, f = max. ind. ? 170 ? 160 ? 140 typ. (2) ? 105 ? 95 ? 75 ind. (@15 ns) ? 90 i sb ttl standby v dd = max., com. ? 55 ? 45 ? 40 ma current v in = v ih or v il ind. ? 55 ? 45 ? 40 (ttl inputs) ce v ih , f = max i sb 1 ttl standby v dd = max., com. ? 25 ? 25 ? 25 ma current v in = v ih or v il ind. ? 30 ? 30 ? 30 (ttl inputs) ce v ih , f = 0 i sb 2 cmos standby v dd = max., com. ? 5 ? 5 ? 5 ma current ce v dd ? 0.2v, ind. ? 10 ? 10 ? 10 typ. (2) ? 0.5 ? 0.5 ? 0.5 (cmos inputs) v in v dd ? 0.2v, or v in 0.2v, f = 0 notes: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.3v, t a = 25 o c. not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. o 07/02/2010 is63lv1024 is63lv1024l ac test loads ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference levels output load see figures 1 and 2 read cycle switching characteristics (1) (over operating range) -8 ns -10 ns -12 ns symbol parameter min. max. min. max. min. max. unit t rc read cycle time 8 ? 10 ? 12 ? ns t aa address access time ? 8 ? 10 ? 12 ns t oha output hold time 2 ? 2 ? 2 ? ns t ace ce access time ? 8 ? 10 ? 12 ns t doe oe access time ? 4 ? 5 ? 6 ns t lzoe (2) oe to low-z output 0 ? 0 ? 0 ? ns t hzoe (2) oe to high-z output 0 4 0 5 0 6 ns t lzce (2) ce to low-z output 3 ? 3 ? 3 ? ns t hzce (2) ce to high-z output 0 4 0 5 0 6 ns t pu ce to power up time 0 ? 0 ? 0 ? ns t pd ce to power down time ? 8 ? 10 ? 12 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v loading specified in figure 1. 2. tested with the loading specified in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. figure 1 output v t = 1.5v z out = 50 50 317 5 pf including jig and scope 351 output 3.3v figure 2
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. o 07/02/2010 is63lv1024 is63lv1024l data valid read1.eps previous data valid t aa t oha t oha t rc d out address t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzce read cycle no. 2 (1,3) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. o 07/02/2010 is63lv1024 is63lv1024l write cycle switching characteristics (1,3) (over operating range) -8 ns -10 ns -12 ns symbol parameter min. max. min. max. min. max. unit t wc write cycle time 8 ? 10 ? 12 ? ns t sce ce to write end 7 ? 7 ? 8 ? ns t aw address setup time to 8 ? 8 ? 8 ? ns write end t ha address hold from 0 ? 0 ? 0 ? ns write end t sa address setup time 0 ? 0 ? 0 ? ns t pwe 1 (1) we pulse width ( oe high) 7 ? 7 ? 8 ? ns t pwe 2 (2) we pulse width ( oe low) 8 ? 10 ? 12 ? ns t sd data setup to write end 5 ? 5 ? 6 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 4 ? 5 ? 6 ns t lzwe (2) we high to low-z output 3 ? 3 ? 3 ? ns notes: 1. test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling ed ge of the signal that terminates the write. ac waveforms write cycle no. 1 (1,2 ( ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. o 07/02/2010 is63lv1024 is63lv1024l ac waveforms write cycle no. 2 (1) ( we controlled, = high during write cycle) ( we controlled: oe is low during write cycle) notes: 1. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe > v ih . data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. o 07/02/2010 is63lv1024 is63lv1024l ( ce controlled) symbol p arameter test condition options min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 2.0 ? 3.6 v i dr data retention current v dd = 2.0v, ce v dd ? 0.2v is63lv1024 ? 0.5 10 ma is63lv1024l ? 0.05 1.5 t sdr data retention setup time see data retention waveform 0 ? ? ns t rdr recovery time see data retention waveform t rc ??ns note 1 : typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. o 07/02/2010 is63lv1024 is63lv1024l speed (ns) order part no. package 8 is63lv1024-8k 400-mil plastic soj IS63LV1024-8KL 400-mil plastic soj, lead-free 10 is63lv1024-10t tsop (type ii) is63lv1024-10j 300-mil plastic soj is63lv1024-10k 400-mil plastic soj 12 is63lv1024-12t tsop (type ii) is63lv1024-12j 300-mil plastic soj is63lv1024-12jl 300-mil plastic soj, lead-free is63lv1024-12kl 400-mil plastic soj, lead-free speed (ns) order part no. package 8 is63lv1024-8ki 400-mil plastic soj 10 is63lv1024-10ki 400-mil plastic soj 12 is63lv1024-12ti tsop (type ii)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. o 07/02/2010 is63lv1024 is63lv1024l speed (ns) order part no. package 8 is63lv1024l-8t tsop (type ii) is63lv1024l-8tl tsop (type ii), lead-free is63lv1024l-8b mbga (8mmx10mm) 10 is63lv1024l-10t tsop (type ii) is63lv1024l-10tl tsop (type ii), lead-free is63lv1024l-10hl stsop (type i) (8mm x13.4mm), lead-free 12 is63lv1024l-12t tsop (type ii) is63lv1024l-12tl tsop (type ii), lead-free is63lv1024l-12h stsop (type i) (8mm x13.4mm) is63lv1024l-12j 300-mil plastic soj is63lv1024l-12jl 300-mil plastic soj, lead-free is63lv1024l-12b mbga (8mmx10mm) speed (ns) order part no. package 8 is63lv1024l-8ti tsop (type ii) is63lv1024l-8ji 300-mil plastic soj is63lv1024l-8ki 400-mil plastic soj is63lv1024l-8bi mbga (8mmx10mm) 10 is63lv1024l-10hi stsop (type i) (8mm x13.4mm) is63lv1024l-10jli 300-mil plastic soj, lead-free is63lv1024l-10kli 400-mil plastic soj, lead-free is63lv1024l-10tli tsop (type ii), lead-free 12 is63lv1024l-12bi mbga (8mmx10mm) is63lv1024l-12bli mbga (8mmx10mm), lead-free is63lv1024l-12ti tsop (type ii) is63lv1024l-12tli tsop (type ii), lead-free speed (ns) top mark order part no. package 8 is63lv1024l-10kli u788b-8kli 400-mil plastic soj, lead-free is63lv1024l-10tli u788a-8tli tsop (type ii), lead-free
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. o 07/02/2010 is63lv1024 is63lv1024l
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. o 07/02/2010 is63lv1024 is63lv1024l note : 2. dimension d and e1 do not include mold protrusion . 4. formed leads shall be planar with respect to one another within 0.1mm 3. dimension b2 does not include dambar protrusion/intrusion. at the seating plane after final test. 1. controlling dimension : mm 5. reference document : jedec spec ms-027. seating plane 12/19/2007
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. o 07/02/2010 is63lv1024 is63lv1024l
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 rev. o 07/02/2010 is63lv1024 is63lv1024l
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. o 07/02/2010 is63lv1024 is63lv1024l note : 2. reference document : jedec mo-207 1. controlling dimension : mm package outline 08/12/2008

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